1. Field of the Invention
The present invention relates to logic circuits, and in particular, to logic circuits in which two or more signal processing functions are performed in parallel, i.e. simultaneously, so as to minimize input-to-output signal propagation delay.
2. Description of the Related Art
In the unending quest for increased performance and operating speed, digital logic designers are constantly analyzing and seeking to optimize the performance characteristics of the circuits used for processing digital logic signals. These circuit performance characteristics, or functions, can be broadly classified as performing "logical work," "electrical work," "communication work," "synchronization work" and "memory work."
Logical work includes those functions by which digital logic signals are logically manipulated or processed, with common examples including multiplexors and Boolean logic gates such as AND, OR, NAND, NOR, etc. Electrical work includes those functions whereby the electrical parameters of the digital logic signals are manipulated or processed, with one common example including signal buffering whereby the load-driving capability of a signal is increased. Communication work includes those functions whereby the various digital logic signals are communicated to their appropriate destinations, with common examples including conductors. Synchronization work includes those functions whereby relative timing between signals is established so that the various logic signals are received and outputted at the desired times, with common examples including work performed by synchronized latches, transmission gates and pass gates. Memory work includes those functions whereby data is stored for later use, with common examples including latches and random access memory (RAM).
Of the foregoing, that which is generally most critical is the logical work, with the remaining circuit functions generally seen as serving as support functions. However, regardless of the relative importance of each of these functions, designers and users have nonetheless sought to increase the performance and speed of each one. However, just as with any function which must be performed by physical processes or elements, physical limits are soon encountered which establish upper limits on performance and operating speed.
Accordingly, it would be desirable to have a technique whereby performance and speed of a logic circuit can be increased irrespective of the physical limits then predominating among the various circuit functions.